As integrated circuit memory devices become more highly integrated, the area of the substrate available for each memory cell is reduced. Accordingly, each memory cell capacitor and memory cell transistor must be fabricated on a smaller area of the substrate. By reducing the area available for the memory cell capacitor, however, it may be difficult to maintain a desired capacitance.
The capacitance C of a capacitor is proportional to the surface area A of the capacitor storage electrode and to the dielectric constant .epsilon. of the dielectric between the capacitor electrodes. The capacitance is inversely proportional to the distance d between the storage electrodes which is also the thickness of the dielectric layer. These relationships are mathematically shown in the following equation: EQU C=.epsilon.(A/d).
Accordingly, memory devices having increased integration densities may have reduced memory cell capacitances.
A memory cell capacitor is used to store a bit of data in a dynamic random access memory device. In particular, the presence of a first predetermined electrical charge indicates a data value of "1", and the presence of a second predetermined electrical charge indicates a data value of "0". Accordingly, the capacitor should be capable of maintaining the predetermined charges without significant variations. In particular, charge variations (causing soft errors) due to external influences such as alpha-particles should be reduced. There is thus a need to maintain a predetermined capacitance for memory cell capacitors despite the reduced substrate areas available for each memory cell capacitor.
Methods for increasing the surface area of a capacitor electrode on a predetermined area of a substrate have thus been explored. In particular, capacitor storage electrodes have been developed having three-dimensional structures such as stack-type electrodes, cylindrical type electrodes, and fin type electrodes. The manufacturing steps used to produce these three-dimensional structures, however, may be undesirably complex.
Alternately, hemispherical grained silicon (HSG-Si) layers have been used to provide capacitor storage electrodes having increased surface areas. These structures can be formed with less complexity than may be required to form the above mentioned three-dimensional structures. A method for forming a hemispherical grained silicon layer will now be discussed with reference to FIG. 1. FIG. 1 is a graph illustrating the process temperatures for steps of a conventional method of forming a hemispherical grained silicon layer. As shown, this method includes three steps: a standby step 10; a seeding step 12; and an annealing step 14. The standby step 10 is used to prepare a wafer used in the formation of the hemispherical grained silicon layer wherein the wafer is heated prior to forming the hemispherical grained silicon layer on the wafer. Before heating the wafer, a capacitor storage electrode is formed on the wafer.
During the seeding step 12, HSG seeds are implanted on the capacitor storage electrode, and these HSG seeds provide nuclei for the formation of the hemispherical grained silicon layer. The seeding step 12 is performed at a temperature t.sub.2 which is the same temperature used during the standby step 10. During the annealing step 14, silicon is grown from the seeds implanted on the wafer to form the hemispherical grained silicon layer. This annealing step is performed at a temperature t.sub.1 which is lower than the temperature t.sub.2 used during the standby step 10 and the seeding step 12.
As discussed above, the standby step 10 and the seeding step 12 are performed at the same temperature when forming a hemispherical grained silicon layer according to the prior art. The capacitor storage electrode may thus be overheated during the standby step 10 thereby resulting in crystallization of the storage electrode. As a result, the quality of the HSG seeds formed during the seeding step 12 may be reduced. Accordingly, it may be difficult to form a stable hemispherical grained silicon layer during the annealing step 14.